The present invention relates to a circuit technology for converting an analog image signal provided by a personal computer or the like into a corresponding digital image signal and displaying a picture represented by the digital image signal on a fixed- pixel display device, such as a liquid crystal panel. More specifically, the present invention relates to a circuit technology for automatically carrying out automatic clock phase adjustment when converting an analog image signal into a corresponding digital image signal.
A liquid crystal display requiring less space and less power has become an attractive picture display for personal computers in recent years. Generally, the liquid crystal display converts an analog image signal provided by a personal computer into a corresponding digital image signal, subjects the digital image signal to image processing process, such as an image expansion process, an image compression process or the like, and displays a picture represented by the digital image signal.
FIG. 5 shows an A/D converter 505 for converting an analog image signal 501 into a corresponding digital image signal, and the waveforms of the analog image signal and clock signals. As *shown in FIG. 5, the analog image signal 501 is converted into a corresponding digital image signal by the A/D converter 505 in synchronism with the clock signal.
The A/D conversion of the analog image signal 501 is carried out in synchronism with the clock signal 502 of a phase 1 and the clock signal 503 of a phase 2.
When the A/D conversion of the analog image signal 501 is executed in synchronism with the clock signal 502 of the phase 1 and the clock signal 503 of the phase 2, the digital image signal provided by the A/D converter 505 is very unstable because the pulses of the clock signals 502 and 503 correspond to a leading edge and a trailing edge of the analog image signal 501, respectively. A picture represented by thus produced digital image signal seems to have noise. The phase of the clock signal must be adjusted as the phase 3 of a clock signal 504 to use a stable portion of the analog image signal for A/D conversion.
The adjustment of a clock signal requires the operator to operate keys, watching a picture displayed on the liquid crystal display. However, work for adjusting the phase of the clock signal while visually observing the variation of the picture is very difficult. A method of automatically adjusting the phase of a clock signal for timing an A/D conversion operation has been developed to avoid such difficult work. An automatic clock phase adjusting function is essential to a liquid crystal display.
An automatic clock phase adjusting method is disclosed in JP- A No. Hei 10-63234. A prior art technology associated with this prior art automatic clock phase adjusting method will be described hereinafter.
FIG. 6 shows a prior art liquid crystal display. A personal computer applies an analog image signal, a horizontal synchronizing signal and a vertical synchronizing signal respectively to an image signal input terminal 101, a horizontal synchronizing signal input terminal 111 and a vertical synchronizing signal input terminal 112.
The analog image signal is given to an A/D converter 102. The A/D converter 102 converts the analog image signal into a corresponding digital image signal in synchronism with a clock signal generated by a clock generating circuit 106. The digital image signal provided by the A/D converter 102 is given to an image processing circuit 103 and an image edge detecting circuit 108.
The image processing circuit 103 processes the input digital image signal for expansion or compression. The digital image signal processed by the image processing circuit 103 is transferred through a liquid crystal driving circuit 104 to a liquid crystal panel 105 to display a picture represented by the digital image signal.
The horizontal synchronizing signal applied to the horizontal synchronizing signal input terminal 111 is given to a delay circuit 110. The delay circuit 110 delays the horizontal synchronizing signal by a delay determined by a control circuit 107. The delayed horizontal synchronizing signal provided by the delay circuit 110 is given to the clock generating circuit 106 and the image edge detecting circuit 108.
The clock generating circuit 106 divides the frequency of the horizontal synchronizing signal by a value determined by the control circuit 107 to generate a clock signal. Thus the clock phase is controlled by the delay of the horizontal synchronizing signal. The clock signal generated by the clock generating circuit 106 is given to the A/D converter 102, the image processing circuit 103 and the image edge detecting circuit 108. The vertical synchronizing signal applied to the vertical synchronizing signal input terminal 112 is given to the image processing circuit 103 and the image edge detecting circuit 108. The control circuit 107 controls the general operations of the liquid crystal display and a principal component of the control circuit is a microcomputer.
The image edge detecting circuit 108 detects the horizontal image starting coordinates and horizontal image terminating coordinates of the digital image signal by using an image level determined by the control circuit 107 as a threshold. The horizontal direction can be detected in a unit of clock on the basis of the horizontal synchronizing signal. The vertical direction can be detected in a unit of line on the basis of the vertical synchronizing signal. The term xe2x80x9ccoordinatesxe2x80x99 used herein signifies a pixel at an edge with respect to a horizontal direction, and a line including the pixel.
A conventional automatic clock phase adjusting operation will be described hereinafter with reference to FIG. 7 showing a conventional clock phase adjusting procedure on an assumption that the clock dividing ratio conforms to the input image signal, i.e., the clock generating circuit 106 provides a clock signal generated by dividing the horizontal synchronizing signal by the total number of horizontal pixels, before the automatic clock phase adjustment is executed.
In step 701, the control circuit 107 determines a minimum delay for the delay circuit 110. In step 702, the control circuit 107 reads data on a horizontal image starting position from the image edge detecting circuit 108 and stores the same in an internal memory. In step 703, the control circuit 107 increases the delay for the delay circuit 110 and delays the clock phase. In step 704, the control circuit 107 reads data on a horizontal image starting position from the image edge detecting circuit 108. In step 705, query is made to see if the horizontal image starting position read in step 704 is different from that read in step 702. If the response in step 705 is affirmative, the control circuit 107 sets a delay equal to half a delay at time corresponding to step 706 as an adjusted value for the delay circuit 110. If the response in step 705 is negative, the program returns to step 703.
FIG. 8 is a waveform diagram showing the waveforms of an analog image signal and a clock signal.
Suppose that a clock phase at time corresponding to step 701 is a clock phase 802 for analog image signal 801. In step 702, a horizontal image starting position n is detected. When steps 703 and 704 are repeated, the clock phase is delayed to a clock phase 803 and then to a clock phase 804. In a state with the clock phase 804, a horizontal image starting position detected in step 704 is nxe2x88x921. In step 705 it is decided that the horizontal image starting position changed from n to nxe2x88x921, and the clock phase 804 is set at a position around the center of a pixel in step 706.
This conventional automatic clock phase adjusting method, however, is effective only with an analog image signal in which a central portion of each pixel is always stable and is unable to achieve automatic clock phase adjustment satisfactorily when an analog image signal has a waveform as shown in FIG. 9. An analog image signal 901 shown in FIG. 9 has a dull waveform and a central portion of a pixel corresponds to a leading edge. Consequently, an unstable digital signal is provided when the analog image signal is subjected to A/D conversion with the clock phase coincided with a central portion of a pixel as a clock phase 902. Therefore, the clock phase needs to be adjusted as a clock phase 903. It is highly possible that an analog image signal having a dull waveform like the analog image signal 901 is given to the liquid crystal display due to the influence of a cable connecting the personal computer to the liquid crystal display or the like. When such an analog image signal having a dull waveform is given to the liquid crystal display, the conventional automatic clock phase adjusting method is unable to adjust clock phase and, consequently, the operator needs to adjust clock phase manually. Thus the conventional automatic clock phase adjusting method is effective only with analog image signals in which a central portion of each pixel is stable.
Accordingly, it is an object of the present invention to provide an automatic clock phase adjusting device capable of automatically achieving optimum clock phase adjustment in conformity to the waveform of an analog image signal.
According to one aspect of the present invention, an automatic clock phase adjusting device comprises: an A/D converter that receives an analog image signal and a clock signal, and converts the analog image signal into a corresponding digital image signal in synchronism with the clock signal; a delay circuit that receives a horizontal synchronizing signal synchronous with the analog image signal and provides the horizontal synchronizing signal after delaying the horizontal synchronizing signal by an optionally determined delay; a clock generating circuit that receives the horizontal synchronizing signal from the delay circuit, divides the frequency of the delayed horizontal synchronizing signal to generate the clock signal; an image edge detecting circuit that receives the digital image signal provided by the A/D converter, the horizontal synchronizing signal provided by the delay circuit, the clock signal provided by the clock generating circuit, and a vertical synchronizing signal synchronous with the analog image signal, and detects a horizontal image starting coordinates and horizontal image terminating coordinates; an image level detecting circuit that receives signals the same as those received by the image edge detecting circuit, and detects a digital image signal indicating specified coordinates; and a control circuit that carries out a first control operation for sequentially delaying the phase of the clock signal generated by the clock generating circuit by changing the delay given to the delay circuit from a minimum value to a value exceeding one period of the clock signal in an optional step, a second control operation for obtaining digital signal values at the horizontal image starting coordinates and the horizontal image terminating coordinates detected by the image edge detecting circuit by the image level detecting circuit in each clock phase specified by the first control operation, an arithmetic operation for adding up the digital signal values of the horizontal image starting coordinates and the horizontal image terminating coordinates in each clock phase obtained by the second control operation, a detecting operation for detecting a clock phase corresponding to a maximum added digital signal value among the added digital signal values calculated by the arithmetic operation, and a third control operation for controlling the delay circuit so that the clock signal has a clock phase detected by the detecting operation.
The automatic clock phase adjusting device is capable of automatically achieving an optimum clock phase adjustment in conformity to the waveform of the input analog image signal.